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1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators AD7262
FEATURES
Dual simultaneous sampling 12-bit, 2-channel ADC True differential analog inputs Programmable gain stage: x1, x2, x3, x4, x6, x8, x12, x16, x24, x32, x48, x64, x96, x128 Throughput rate per ADC 1 MSPS for AD7262 500 kSPS for AD7262-5 Analog input impedance: >1 G Wide input bandwidth -3 dB bandwidth: 1.7 MHz at gain = 2 4 on-chip comparators SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 Device offset calibration, system gain calibration On-chip reference: 2.5 V -40C to +105C operation High speed serial interface SPI/QSPITM/MICROWIRETM/DSP compatible 48-lead LFCSP and LQFP packages
FUNCTIONAL BLOCK DIAGRAM
AVCC VREF A
REF
BUF 12-BIT SUCCESSIVE APPROXIMATION ADC
AD7262
OUTPUT DRIVERS
VA + VA-
PGA
T/H
DOUTA
CONTROL LOGIC
SCLK CAL CS REFSEL G0 G1 G2 G3 VDRIVE OUTPUT DRIVERS DOUTB PD0/DIN PD1 PD2
VB+ VB-
PGA
T/H
12-BIT SUCCESSIVE APPROXIMATION ADC BUF
VREF B CA_CBVCC CA+ CA - CB+ CB - CA_CB_GND CC_CDVCC CC+ CC - CD+ CD - CC_CD_GND COMP COMP OUTPUT DRIVERS OUTPUT DRIVERS COUTA COUTB
GENERAL DESCRIPTION
The AD7262/AD7262-5 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates of up to 1 MSPS per on-chip ADC. The AD7262-5 features throughput rates of up to 500 kSPS. Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: x1, x2, x3, x4, x6, x8, x12, x16, x24, x32, x48, x64, x96, and x128. The AD7262/AD7262-5 contain four comparators. Comparator A and Comparator B are optimized for low power, while Comparator C and Comparator D have fast propagation delays. The AD7262/AD7262-5 feature a calibration function to remove any device offset error and programmable gain adjust registers to allow for input path (for example, sensor) offset and gain compensation. The AD7262/AD7262-5 have an on-chip 2.5 V reference that can be disabled if an external reference is preferred. The AD7262/AD7262-5 are ideally suited for monitoring small amplitude signals from a variety of sensors. They include all the functionality needed for monitoring the position feedback signals from a variety of analog encoders used in motor control systems.
COMP
OUTPUT DRIVERS OUTPUT DRIVERS
COUTC COUTD
COMP
AGND
DGND
Figure 1.
PRODUCT HIGHLIGHTS
1. 2. Integrated PGA with a variety of flexible gain settings to allow detection and conversion of low level analog signals. Each PGA is followed by a dual simultaneous sampling ADC, featuring throughput rates of 1 MSPS per ADC for the AD7262. The conversion results of both ADCs are simultaneously available on separate data lines or in succession on one data line if only one serial port is available. Four integrated comparators that can be used to count signals from pole sensors in motor control applications. Internal 2.5 V reference.
3. 4.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07606-001
AD7262 TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 6 Timing Diagram ........................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 Circuit Information .................................................................... 15 Comparators................................................................................ 15 Operation..................................................................................... 15 Analog Inputs .............................................................................. 15 VDRIVE ............................................................................................ 16 Reference ..................................................................................... 17 Typical Connection Diagrams .................................................. 17 Application Details ..................................................................... 20 Modes of Operation ....................................................................... 22 Pin-Driven Mode ....................................................................... 22 Gain Selection ............................................................................. 22 Power-Down Modes .................................................................. 22 Control Register ......................................................................... 23 On-Chip Registers ...................................................................... 24 Serial Interface ................................................................................ 25 Calibration ....................................................................................... 27 Internal Offset Calibration ........................................................ 27 Adjusting the Offset Calibration Registers ................................. 28 System Gain Calibration............................................................ 28 Microprocessor Interfacing ........................................................... 29 AD7262/AD7262-5 to ADSP-BF53x ....................................... 29 Application Hints ........................................................................... 30 Grounding and Layout .............................................................. 30 PCB Design Guidelines for LFCSP .......................................... 30 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
7/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7262 SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = -40C to +105C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE 1 Signal-to-Noise Ratio (SNR) 2 Signal-to-(Noise + Distortion) Ratio (SINAD)2 Total Harmonic Distortion (THD)2 Spurious-Free Dynamic Range (SFDR)2 Common-Mode Rejection Ratio (CMRR) 3 Min 70 70 Typ 73 72 -85 -97 -76 -77 Max Unit dB dB dB dB dB Test Conditions/Comments fIN = 100 kHz sine wave PGA gain setting = 2
For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 @ -3 dB; PGA gain setting = 128 @ -3 dB; PGA gain setting = 2
ADC-to-ADC Isolation3 Bandwidth3 DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Match Zero Code Error2 Zero Code Error Match Negative Full-Scale Error2 Negative Full-Scale Error Match Zero Code Error Drift ANALOG INPUT Input Voltage Range, VIN+ and VIN- Common-Mode Voltage Range, VCM
-90 1.2 1.7 12 1 0.99 0.305
dB MHz MHz Bits LSB LSB % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR V/C V V V V V A pF G V V A pF ppm/C V rms
0.5 0.5 0.122 0.018 0.061 0.092 0.012 0.061 0.122 0.018 0.061 2.5
Guaranteed no missed codes to 12 bits Pregain calibration Postgain calibration Preoffset and pregain calibration Postoffset and postgain calibration Pregain calibration Postgain calibration
0.244
0.305
VCM VCM - 100 mV (VCC/2) - 0.4 (VCC/2) - 0.4 (VCC/2) - 0.6
VREF 2 x Gain VCM + 100 mV (VCC/2) + 0.2 (VCC/2) + 0.4 (VCC/2) + 0.8 1
VCM = AVCC/2; PGA gain setting 2 VCM = 2; PGA gain setting = 1; see Figure 19 4 VCM = AVCC/2; PGA gain setting = 2 VCM = AVCC/2; 3 PGA gain setting 32 VCM = AVCC/2; PGA gain setting 48
DC Leakage Current Input Capacitance3 Input Impedance3 REFERENCE INPUT/OUTPUT Reference Output Voltage 5 Reference Input Voltage Range DC Leakage Current Input Capacitance3 VREFA, VREFB Output Impedance3 Reference Temperature Coefficient VREF Noise3
0.001 5 1 2.495 2.5 2.5 0.3 20 4 20 20
2.505 1
2.5 V 5 mV max @ 25C External reference applied to Pin VREFA/Pin VREFB
Rev. 0 | Page 3 of 32
AD7262
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate COMPARATORS Input Offset Comparator A and Comparator B Comparator C and Comparator D Offset Voltage Drift Input Common-Mode Range3 Input Capacitance3 Input Impedance3 IDD Normal Mode (Static) 6 Comparator A and Comparator B Comparator C and Comparator D Propagation Delay Time High to Low, tPHL Comparator A and Comparator B Comparator C and Comparator D Low to High, tPLH Comparator A and Comparator B Comparator C and Comparator D Delay Matching Comparator A and Comparator B Comparator C and Comparator D 250 10 ns ns Min 0.7 x VDRIVE 0.8 1 4 VDRIVE - 0.2 0.4 1 5 Twos complement 19 x tSCLK 400 1 500 Typ Max Unit V V A pF V V A pF Test Conditions/Comments
VIN = 0 V or VDRIVE
ns ns MSPS kSPS
AD7262 AD7262-5
2 2 0.5 0 to 4 0 to 1.7 4 1
4 4
mV mV V/C V V pF G
TA = 25C to 105C only All comparators CA_CBVCC = 5 V CA_CBVCC = 2.7 V
3 6 60 120
8.5 170
A A A A
25 pF load, COUTx = 0 V, VCM = AVCC/2, VOVERDRIVE = 200 mV differential CA_CBVCC = 3.3 V CA_CBVCC = 5.25 V CC_CDVCC = 3.3 V CC_CDVCC = 5.25 V VCM = AVCC/2, VOVERDRIVE = 200 mV differential CA_CBVCC = 2.7 V CA_CBVCC = 5 V CC_CDVCC = 2.7 V CC_CDVCC = 5 V CA_CBVCC = 2.7 V CA_CBVCC = 5 V CC_CDVCC = 2.7 V CC_CDVCC = 5 V VCM = AVCC 2, VOVERDRIVE = 200 mV differential
1.4 0.95 0.20 0.13 2 0.93 0.18 0.12
3.5 0.32
s s s s s s s s
4 0.28
Rev. 0 | Page 4 of 32
AD7262
Parameter POWER REQUIREMENTS AVCC CA_CBVCC, CC_CDVCC VDRIVE IDD ADC Normal Mode (Static) ADC Normal Mode (Dynamic) Shutdown Mode Power Dissipation ADC Normal Mode (Static) ADC Normal Mode (Dynamic) Shutdown Mode
1 2 3
Min 4.75 2.7 2.7
Typ
Max 5.25 5.25 5.25
Unit V V V mA mA A
Test Conditions/Comments Digital inputs = 0 V or VDRIVE
20 23 0.5
31.5 33.3 1
AVCC = 5.25 V AVCC = 5.25 V AVCC = 5.25 V, ADCs and comparators powered down
105 120 2.625
165 175 5.25
mW mW W
These specifications were determined without the use of the gain calibration feature. See the Terminology section. Samples tested during initial release to ensure compliance; they are not subject to production testing. 4 For PGA gain = 1; to use the full analog input range (VCM VREF/2) of the AD7262, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V. 5 Refers to Pin VREFA or Pin VREFB. 6 This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by two.
Rev. 0 | Page 5 of 32
AD7262
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted. 1 Table 2.
Parameter fSCLK Limit at TMIN, TMAX 2.7 V VDRIVE 3.6 V 4.75 V VDRIVE 5.25 V 200 200 40 40 32 32 20 20 19 x tSCLK 19 x tSCLK 475 475 950 950 13 13 10 15 29 15 0.4 x tSCLK 0.4 x tSCLK 13 13 5 35 2 2 3 3 240 15 10 15 23 13 0.4 x tSCLK 0.4 x tSCLK 13 13 5 35 2 2 3 3 240 15 Unit kHz min MHz max MHz typ MHz max ns max ns max ns max ns min ns min ns max ns max ns min ns min ns min ns min ns max ns min ns max s min s min ns min ns min s max s max Description AD7262 2 AD72622 AD7262-5 tSCLK = 1/fSCLK AD7262 AD7262-5 Minimum time between end of serial read/bus relinquish and next falling edge of CS CS to SCLK setup time Delay from 19th SCLK falling edge until DOUTA and DOUTB are three-state disabled Data access time after SCLK falling edge SCLK to data valid hold time SCLK high pulse width SCLK low pulse width CS rising edge to falling edge pulse width CS rising edge to DOUTA, DOUTB, high impedance/bus relinquish SCLK falling edge to DOUTA, DOUTB, high impedance SCLK falling edge to DOUTA, DOUTB, high impedance Minimum CAL pin high time Minimum time between the CAL pin high and the CS falling edge DIN setup time prior to SCLK falling edge DIN hold time after SCLK falling edge Internal reference, with a 1 F decoupling capacitor With an external reference, 10 s typical
tCONVERT
tQUIET t2 t3 3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 tPOWER-UP
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVCC) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section. 2 See the Serial Interface section. 3 The time required for the output to cross 0.4 V or 2.4 V.
TIMING DIAGRAM
CS
t8 t2 t6
2 3 4 5 18 19 20 21 29 30 31 1
SCLK
t3
DOUTA THREE-STATE DB11 A
t7
t4
DB10 A DB9A
t5
DB1A
t9
DB0A
tQUIET
THREESTATE THREESTATE
07606-002
DOUTB
THREE-STATE
DB11 B
DB10 B
DB9B
DB1B
DB0B
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 6 of 32
AD7262 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDRIVE to DGND VDRIVE to AGND AVCC to AGND/DGND CA_CBVCC to CA_CB_GND CC_CDVCC to CC_CD_GND AGND to DGND CA_CB_GND/CC_CD_GND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND VREFA/VREFB Input to AGND COUTA/COUTB/COUTC/COUTD to GND CA/CB/CC/CD to CA_CB_GND/CC_CD_GND Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Package JA Thermal Impedance JC Thermal Impedance LQFP Package JA Thermal Impedance JC Thermal Impedance Pb-Free Temperature, Soldering Reflow ESD Rating -0.3 V to AVCC -0.3 V to AVCC -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to AVCC + 0.3 V -0.3 V to +7 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVCC + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to CA_CBVCC/CC_CDVCC + 0.3 V -40C to +105C -65C to +150C 150C 30C/W 3C/W 55C/W 16C/W 255C 2 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 7 of 32
AD7262 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CB- CA_CB_GND VREF A
CA+ CA- CB+ CB- CA_CB_GND VREF A
AGND
AVCC
CA+
CB+
CA-
AGND AVCC
G0
G1
G2
CA_CBVCC 1 AVCC 2 VA- 3 VA+ 4 AGND 5 AGND 6 AVCC 7 AGND 8
VB+ 9
PIN 1 INDICATOR
36 35 34 33
CAL CS SCLK AVCC DOUTA DOUTB COUTA COUTB DGND VDRIVE COUTC COUTD
CA_CBVCC AVCC VA- VA+ AGND AGND AVCC AGND VB+ VB- AVCC CC_CDVCC 1 2 3 4 5 6 7 8 9 10 11 12
PIN 1 INDICATOR
48 47 46 45 44 43 42 41 40 39 38 37
48 47 46 45 44 43 42 41 40 39 38 37
G3
G0 G1 G2 G3
AD7262
TOP VIEW (Not to Scale)
32 31 30 29 28 27 26 25
AD7262
TOP VIEW (Not to Scale)
VB- 10 AVCC 11 CC_CDVCC 12
13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
CAL CS SCLK AVCC DOUTA DOUTB COUTA COUTB DGND VDRIVE COUTC COUTD
CC_CD_GND VREF B
PD0/DIN
CC+
CD+
REFSEL
CC-
CD-
AGND
PD2
AVCC
PD1
07606-003
CC+ CC- CD+ CD- CC_CD_GND VREF B
PD2 PD1 PD0/DIN
NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS.
REFSEL
AGND AVCC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 48-Lead LQFP Pin Configuration
Figure 4. 48-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 2, 7, 11, 20, 33, 41 Mnemonic AVCC Description Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the AD7262/AD7262-5. All AVCC pins can be tied together. This supply should be decoupled to AGND with a 100 nF ceramic capacitor per supply and a 10 F tantalum capacitor. Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be tied together. Analog Inputs of ADC A. True differential input pair. Analog Inputs of ADC B. True differential input pair. Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the internal reference buffer for each respective ADC. Typically, 1 F capacitors are required to decouple the reference. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7262/AD7262-5. This clock is also used as the clock source for the conversion process. A minimum of 31 clocks is required to perform the conversion and access the 12-bit result. Logic Input. Initiates an internal offset calibration. Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD1 and PD0 pins (see Table 7). Logic Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD0 pins (see Table 7).
1
CA_CBVCC
12
CC_CDVCC
4, 3 9, 10 43, 18
VA+, VA- VB+, VB- VREFA, VREFB
34
SCLK
36 21 22
CAL PD2 PD1
Rev. 0 | Page 8 of 32
07606-004
AD7262
Pin No. 23 Mnemonic PD0/DIN Description Logic Input/Data Input. Places the AD7262/AD7262-5 in selected shutdown mode in conjunction with the PD2 and PD1 pins (see Table 7). If all gain selection pins, G0 to G3, are tied low, this pin acts as the data input pin, and all programming is via the control register (see Table 8). Data to be written to the AD7262/AD7262-5 control register is provided on this input and is clocked into the register on the falling edge of SCLK. Chip Select. Active low logic input. This input initiates conversions on the AD7262/AD7262-5. Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A and Comparator B. These two comparators have very low power consumption. Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C and Comparator D. This pair of comparators offers very fast propagation delays. Analog Ground. Ground reference point for all analog circuitry on the AD7262/AD7262-5. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should connect to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and CC_CD_GND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND. Digital Ground. This is the ground reference point for all digital circuitry on the AD7262/AD7262-5. The DGND pin should be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective comparator. These are digital output pins with logic levels determined by the VDRIVE supply. Serial Data Outputs. The data output from the AD7262/AD7262-5 is supplied to each pin as a serial data stream in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of 31 SCLKs is required to perform the conversion and access the 12-bit data. During the conversion process, the data output pins are in three-state and, when the conversion is completed, the 19th SCLK edge clocks out the MSB. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for an additional 12 SCLK cycles on either DOUTA or DOUTB following the initial 31 SCLKs, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four pins are tied low, the PD0 pin acts as a data input pin, DIN, and all programming is made via the control register (see Table 6). Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what voltage the interface operates, including the comparator outputs. This pin should be decoupled to DGND. Comparator Ground. This is the ground reference point for all comparator circuitry on the AD7262/ AD7262-5. Both the CA_CB_GND pin and the CC_CD_GND pin should connect to the GND plane of a system and can be tied to AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the onchip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7262/AD7262-5 through the VREFA and/or VREFB pin.
35 48, 47, 46, 45 13, 14, 15, 16 5, 6, 8, 19, 42
CS CA+, CA-, CB+, CB- CC+, CC-, CD+, CD- AGND
28
DGND
30, 29, 26, 25 32, 31
COUTA, COUTB, COUTC, COUTD DOUTA, DOUTB
40, 39, 38, 37
G0, G1, G2, G3
27
VDRIVE
44, 17
CA_CB_GND, CC_CD_GND
24
REFSEL
Rev. 0 | Page 9 of 32
AD7262 TYPICAL PERFORMANCE CHARACTERISTICS
0.6 0.4 AVCC = 5V VDRIVE = 5V fS = 1MSPS TA = 25C INTERNAL REFERENCE PGA GAIN = 2
DNL ERROR (LSB)
0.6
0.4
DNL ERROR (LSB)
0.2
0.2
AVCC = 5V VDRIVE = 5V fS = 1MSPS TA = 25C INTERNAL REFERENCE PGA GAIN = 32
0
0
-0.2
-0.2
-0.4
-0.4
07606-005
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
Figure 5. Typical DNL at Gain of 2
Figure 8. Typical DNL at Gain of 32
1.0 0.8 0.6 0.4
INL ERROR (LSB)
INL ERROR (LSB)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
07606-006
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 AVCC = 5V VDRIVE = 5V fS = 1MSPS TA = 25C INTERNAL REFERENCE PGA GAIN = 2 500 1000 1500 2000 CODE 2500 3000 3500 4000
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
Figure 6. Typical INL at Gain of 2
Figure 9. Typical INL at Gain of 32
0 -20 -40 -60
(dB)
AVCC = 5V VDRIVE = 2.7V fS = 1MSPS TA = 25C fIN = 100kHz INTERNAL REFERENCE SNR = 73dB, THD = -82.5dB PGA GAIN = 2
(dB)
0 -20 -40 -60 -80 -100 -120 -140 0 50k
AVCC = 5V VDRIVE = 5V fS = 1MSPS TA = 25C fIN = 100kHz INTERNAL REFERENCE SNR = 68.38dB, THD = -82dB PGA GAIN = 32
-80 -100 -120 -140 0 50k 100k 150k 200k 250k 300k 350k 400k 450k FREQUENCY (Hz)
07606-007
100k 150k 200k 250k 300k 350k 400k 450k 500k FREQUENCY (Hz)
Figure 7. 3 dB Typical FFT at Gain of 2
Figure 10. Typical FFT at Gain of 32
Rev. 0 | Page 10 of 32
07606-010
07606-009
-1.0
AVCC = 5V VDRIVE = 5V fS = 1MSPS TA = 25C INTERNAL REFERENCE PGA GAIN = 32
07606-008
-0.6
-0.6
AD7262
9000 8839 8000 7000
NUMBER OF HITS
2.4968 2.4967 2.4966 2.4965 2.4964 2.4963
6000
VREF (V)
5000 4000 3000 2000 1000 0 0 2043 2044 CODE 828 333 2045 0
07606-011
2.4962 2.4961
AVCC = 5V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE
07606-014
0
20
40
60
80
100
120
140
160
180
200
CURRENT LOAD (A)
Figure 11. Histogram of Codes for 10k Samples at Gain of 2
Figure 14. VREF vs. Reference Output Current Load
8000 7000 6000 3dB BANDWIDTH (kHz)
NUMBER OF HITS
1900
6967
1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 AVCC = 5V VDRIVE = 5V fS = 1MSPS INTERNAL REFERENCE 1 2 3 4 6 8 12 16 24 32 48 64 96 128
07606-015 07606-016
5000 4000 3000 2000 1297 1000 0 0 2044 2045 2046 2047 CODE 4 2048 0 2049
07606-012
1732
700 600
GAIN
Figure 12. Histogram of Codes for 10k Samples at Gain of 32
Figure 15. 3 dB Bandwidth vs. Gain
-50 -55 -60 -65
THD (dB)
80
AVCC = 5V VDRIVE = 5V fS = 1MSPS INTERNAL REFERENCE
75 70 65
SNR (dB)
GAIN = 32
60 55 50 45 40 AVCC = 5V VDRIVE = 5V fS = 1MSPS INTERNAL REFERENCE FIN = 100kHz 1 2 3 4 6 8 12 16 24 32 48 64 96 128
-70 -75 -70 -85 -90 10
GAIN = 2
35
07606-013
30
110
210
310
410
510
610
710
810
910
ANALOG INPUT FREQUENCY (kHz)
PGA GAIN
Figure 13. THD vs. Analog Input Frequency up to 1 MHz at Gain of 2 and 32
Figure 16. SNR vs. PGA Gain for an Analog Input Tone of 100 kHz
Rev. 0 | Page 11 of 32
AD7262
-90 -88 -86 -84
10 9 8
PROPAGATION DELAY (s)
AVCC = 5V VDRIVE = 3.3V TA = 25C H TO L, H TO L, H TO L, H TO L, L TO H, L TO H, L TO H, L TO H, CA_CBVCC CA_CBVCC CA_CBVCC CA_CBVCC CA_CBVCC CA_CBVCC CA_CBVCC CA_CBVCC = 3.6V = 4.5V = 2.7V = 5V = 2.7V = 3.6V = 4.5V = 5V
7 6 5 4 3 2 1
CMR (dB)
-82 -80 -78 -76 -74 -72 -70 1 2 3 4 6 8 12 16 AVCC = 5V VDRIVE = 5V fS = 1MSPS INTERNAL REFERENCE fRIPPLE = 50kHz
07606-017
24
32
48
64
96 128
0
10
20
30
40
50
60
70
80
90
100
GAIN
OVERDRIVE VOLTAGE (mV)
Figure 17. Common-Mode Rejection vs. Gain
Figure 20. Propagation Delay for Comparator A and Comparator B vs. Overdrive Voltage for Various Supply Voltages
2.0 1.8 1.6
PROPAGATION DELAY (s)
-80 -79 -78 -77
AVCC = 5V VDRIVE = 3.3V TA = 25C
1.4 1.2 1.0 0.8 0.6 0.4 0.2
CMR (dB)
-76 -75 -74 -73 -72 -71 -70 0 20 40 60 80 100 AVCC = 5V VDRIVE = 5V fS = 1MSPS VRIPPLE = 700mV p-p GAIN = 2 INTERNAL REFERENCE
07606-018
L TO H, L TO H, L TO H, L TO H, H TO L, H TO L, H TO L, H TO L,
CC_CDVCC CC_CDVCC CC_CDVCC CC_CDVCC CC_CDVCC CC_CDVCC CC_CDVCC CC_CDVCC
= 2.7V = 3.6V = 4.5V = 5V = 2.7V = 3.6V = 5V = 4.5V
120
140
160
180
200
0
10
20
30
40
50
60
70
80
90
100
RIPPLE FREQUENCY (kHz)
OVERDRIVE VOLTAGE (mV)
Figure 18. Common-Mode Rejection vs. Common-Mode Ripple Frequency
Figure 21. Propagation Delay for Comparator C and Comparator D vs. Overdrive Voltage for Various Supply Voltages
-70 -75
-10 -20 -30 -40 -50 -60
AVCC = 5V VDRIVE = 5V fS = 1MSPS INTERNAL REFERENCE fIN = 100kHz
GAIN 1 GAIN 2
-80 -85
PSRR (dB)
VDRIVE = 5V GAIN = 2 TA = 25C INTERNAL REFERENCE 100mV p-p SINE WAVE ON AVCC AVCC DECOUPLED WITH 10F AND 100nF CAPACITORS
THD (dB)
-90 -95 -100 -105 -110 -115
GAIN 3 -70 GAIN 8 -80 -90 GAIN 12 -100 1.3 1.5 1.7 1.9 GAIN 24 2.1 2.3 2.5 GAIN 32 2.7 2.9 3.1 3.3 GAIN 6
07606-019
GAIN 4
GAIN 16
3.5
3.7
0
200
400
600
800
1000
VCM RANGE (V)
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 19. THD vs. Common-Mode Range for Various PGA Gain Settings
Figure 22. Power Supply Rejection Ratio vs. Supply Ripple Frequency?
Rev. 0 | Page 12 of 32
07606-022
-120
07606-021
0
07606-020
0
AD7262
300 COUTA/COUTB SINK CURRENT COUTC/COUTD SINK CURRENT DOUT SINK CURRENT 100
200
VOUT (V) OR VDD - VOUT (mV)
0
-100 DOUT SOURCE CURRENT -200 COUTA/COUTB SOURCE CURRENT COUTC/COUTD SOURCE CURRENT -300
07606-023
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 CURRENT (mA)
Figure 23. DOUT and COUT Source and Sink Current
Rev. 0 | Page 13 of 32
AD7262 TERMINOLOGY
Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a single (1) LSB point below the first code transition and full scale, a single (1) LSB point above the last code transition. Zero Code Error This is the deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, that is, VCM - 1/2 LSB. Positive Full-Scale Error This is the deviation of the last code transition (011 ... 110) to (011 ... 111) from the ideal, that is, Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7262/AD7262-5, it is defined as THD(dB) = 20 log V2 2 + V3 2 + V 4 2 + V5 2 + V6 2 V1
where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.
Peak Harmonic or Spurious Noise Peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. ADC-to-ADC Isolation ADC-to-ADC isolation is a measure of the level of crosstalk between the ADC A and ADC B. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 40 kHz signal. The figure given is the worst case. PSRR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 22). Propagation Delay Time, Low to High (tPLH) Propagation delay time from low to high is defined as the time taken from the 50% point on a low to high input signal until the digital output signal reaches 50% of its final low value. Propagation Delay Time, High to Low (tPHL) Propagation delay time from high to low is defined as the time taken from the 50% point on a high to low input signal until the digital output signal reaches 50% of its final high value. Comparator Offset Comparator offset is the measure of the density of digital 1s and 0s in the comparator output when the negative analog terminal of the comparator input is held at a static potential and the analog input to the positive terminal of the comparators is varied proportionally about the static negative terminal voltage.
VREF VCM + - 1 LSB 2 x Gain after the zero code error has been adjusted out.
Negative Full-Scale Error This is the deviation of the first code transition (10 ... 000) to (10 ... 001) from the ideal, that is,
VREF VCM - + 1 LSB 2 x Gain after the zero code error has been adjusted out.
Zero Code Error Match This is the difference in zero code error across both ADCs. Positive Full-Scale Error Match This is the difference in positive full-scale error across both ADCs. Negative Full-Scale Error Match This is the difference in negative full-scale error across both ADCs. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 LSB, after the end of a conversion. Signal-to-(Noise + Distortion) Ratio This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the analog-to-digital converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 86 dB.
Rev. 0 | Page 14 of 32
AD7262 THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7262/AD7262-5 are fast, dual, simultaneous sampling, differential, 12-bit, serial ADCs. The AD7262/ AD7262-5 contain two on-chip differential programmable gain amplifiers, two track-and-hold amplifiers, and two successive approximation analog-to-digital converters with a serial interface with two separate data output pins. The AD7262/ AD7262-5 also include four on-chip comparators. They are housed in 48-lead LFCSP and LQFP packages, offering the user considerable space-saving advantages over alternative solutions. The AD7262/AD7262-5 require a low voltage 5 V 5% AVCC to power the ADC core and supply the digital power, a 5.25 V to 2.7 V CA_CBVCC, CC_CDVCC supply for the comparators, and a 2.7 V to 5.25 V VDRIVE supply for interface power. The on-board PGA allows the user to select from 14 programmable gain stages: x1, x2, x3, x4, x6, x8, x12, x16, x24, x32, x48, x64, x96, and x128. The PGA accepts fully differential analog signals. The gain can be selected either by setting the logic state of the G0 to G3 pins or by programming the control register. The serial clock input accesses data from the part while also providing the clock source for each successive approximation ADC. The AD7262/AD7262-5 have an on-chip 2.5 V reference that can be disabled when an external reference is preferred. If the internal reference is used elsewhere in a system, the output from VREFA and VREFB must first be buffered. If the internal reference is the preferred option, the user must tie the REFSEL pin to a logic high voltage. Alternatively, if REFSEL is tied to GND, an external reference can be supplied to both ADCs through the VREFA and VREFB pins (see the Reference section). The AD7262/AD7262-5 also feature a range of power-down options to allow the user great flexibility with the independent circuit components while allowing for power savings between conversions. The power-down feature is implemented via the control register or the PD0 to PD2 pins, as described in the Control Register section. Each pair of comparators operates from its own independent supply, CA_CBVCC and CC_CDVCC. The comparators are specified for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC and CC_CDVCC can be tied to the AVCC supply. The four comparators on the AD7262/AD7262-5 are functional with CA_CBVCC/ CC_CDVCC greater than or equal to 1.8 V. However, no specifications are guaranteed for comparator supplies less than 2.7 V. The wide range of supply voltages ensures that the comparators can be used in a variety of battery backup modes. The four on-chip comparators on the AD7262/AD7262-5 are ideally suited for monitoring signals from pole sensors in motor control systems. The comparators can be used to monitor signals from Hall effect sensors or the inner tracks from an optical encoder. One of the comparators can be used to count the index marker or z marker, which is used on startup to place the motor in a known position.
OPERATION
The AD7262/AD7262-5 have two successive approximation ADCs, each based around two capacitive DACs and two programmable gate amplifiers. The ADC itself comprises control logic, a SAR, and two capacitive DACs. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor amplifiers to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Each ADC is preceded by its own programmable gain stage. The PGA features high analog input impedance, true differential analog inputs that allow the output from any source or sensor to be connected directly to the PGA inputs without any requirement for additional external buffering. The variable gain settings ensure that the device can be used for amplifying signals from a variety of sources. The AD7262/AD7262-5 offer the flexibility to choose the most appropriate gain setting to use the wide dynamic range of the device.
COMPARATORS
The AD7262/AD7262-5 have four on-chip comparators. Comparator A and Comparator B have ultralow power consumption, with static power consumption typically less than 10 W with a 3.3 V supply. Comparator C and Comparator D feature very fast propagation delays of 130 ns for a 200 mV differential overdrive. These comparators have push-pull output stages that operate from the VDRIVE supply. This feature allows operation with a minimum amount of power consumption.
ANALOG INPUTS
Each ADC in the AD7262/AD7262-5 has two high impedance differential analog inputs. Figure 24 shows the equivalent circuit of the analog input structure of the AD7262/AD7262-5. It consists of a fully differential input amplifier that buffers the analog input signal and provides the gain selected by using the gain pins or the control register.
Rev. 0 | Page 15 of 32
AD7262
The two diodes provide ESD protection. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. Exceeding 300 mV causes these diodes to become forward-biased and to start conducting current into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The C1 capacitors in Figure 24 are typically 5 pF and can primarily be attributed to pin capacitance.
VDD
When a full-scale step input is applied to either differential input on the AD7262/AD7262-5 while the other analog input is held at a constant voltage, 3 s of settling time is typically required prior to capturing a stable digital output code.
Transfer Function
The AD7262/AD7262-5 output is twos complement, and the ideal transfer characteristic is shown in Figure 25. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected. The LSB size for the AD7262/AD7262-5 is shown in the following equation:
VREF VREF VCM + - VCM - 2 x Gain 2 x Gain 2x 4096
VIN+ C1
AMP
VOUT+
VDD AMP VIN- C1 VOUT -
07606-024
Figure 24. Analog Input Structure
011...111 011...110
The AD7262/AD7262-5 can accept differential analog inputs from
ADC CODE
V V VCM - REF to VCM + REF 2 x Gain 2 x Gain Table 5 details the analog input range for the AD7262/AD7262-5 for the various PGA gain settings. Here, VREF = 2.5 V and VCM = 2.5 V (AVCC/2, with AVCC = 5 V).
Table 5. Analog Input Range for Various PGA Gain Settings
PGA Gain Setting 1 2 3 4 6 8 12 16 24 32 48 64 96 128
1
000...001 000...000 111...111
100...010 100...001 100...000 0V (VCM - (FSR/2)) + 1LSB (VCM + (FSR/2)) - 1LSB ANALOG INPUT
07606-025
Analog Input Range for VIN+ and VIN- 0.75 V to 3.25 V1 1.875 V to 3.125 V 2.083 V to 2.916 V 2.187 V to 2.813 V 2.292 V to 2.708 V 2.344 V to 2.656 V 2.396 V to 2.604 V 2.422 V to 2.578 V 2.448 V to 2.552 V 2.461 V to 2.539 V 2.474 V to 2.526 V 2.480 V to 2.520 V 2.487 V to 2.513 V 2.490 V to 2.510 V
NOTES 1. FULL-SCALE RANGE (FSR) = VIN+ - VIN-.
Figure 25. Twos Complement Transfer Function
VDRIVE
The AD7262/AD7262-5 have a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC and the comparators to easily interface to both 3 V and 5 V processors. For example, when the AD7262/AD7262-5 are operated with AVCC = 5 V, the VDRIVE pin can be powered from a 3 V supply, allowing a large analog input range with low voltage digital processors.
For VCM = 2 V. If VCM = AVCC /2, the analog input range for VIN+ and VIN- is 1.6 V to 3.4 V.
Rev. 0 | Page 16 of 32
AD7262
REFERENCE
The AD7262/AD7262-5 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The logic state of the REFSEL pin determines whether the internal reference is used. The internal reference is selected for both ADCs when the REFSEL pin is tied to logic high. If the REFSEL pin is tied to AGND, an external reference can be supplied through the VREFA and/or VREFB pins. On power-up, the REFSEL pin must be tied to either a low or high logic state for the part to operate. Suitable reference sources for the AD7262/AD7262-5 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When the AD7262/AD7262-5 are operated in internal reference mode, the 2.5 V internal reference is available at the VREFA and VREFB pins, which should be decoupled to AGND using a 1 F capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 90 A of current when the converter is static. If the internal reference operation is required for the ADC conversion, the REFSEL pin must be tied to logic high on power-up. The reference buffer requires 240 s to power up and charge the 1 F decoupling capacitor during the power-up time.
TYPICAL CONNECTION DIAGRAMS
Figure 26 and Figure 27 are typical connection diagrams for the AD7262/AD7262-5. In these configurations, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7262/AD7262-5 are true differential and have an input impedance in excess of 1 G; thus, no driving op amps are required. The AD7262/AD7262-5 can operate with either an internal or an external reference. In Figure 26, the AD7262/AD7262-5 are configured to operate in control register mode; thus, G0 to G3, PD1, and PD2 can be connected to ground (low logic state). Figure 27 has the gain pins configured for a gain of 2 setup; thus, the device is in pin-driven mode. Both circuit configurations illustrate the use of the internal 2.5 V reference The CA_CBVCC and the CC_CDVCC pins can be connected to either a 3 V or a 5 V supply voltage. The AVCC pin must be connected to a 5 V supply. All supplies should be decoupled with a 100 nF capacitor at the device pin, and some supply sources may require a 10 F capacitor where the source is supplied to the circuit board. The VDRIVE pin is connected to the supply voltage of the microprocessor. The voltage applied to the VDRIVE input controls the voltage of the serial interface. VDRIVE can be set to 3 V or 5 V.
Rev. 0 | Page 17 of 32
AD7262
ANALOG SUPPLY +5V 10F1 100nF 100nF 100nF 100nF 100nF 100nF 10F1 COMPARATOR SUPPLY 3V TO 5V2 100nF
100nF 17 44 5
CC-CD-GND CA-CB-GND AGND
6
AGND
8 19 42 28 2
AGND AGND AGND DGND
7 11 20 41 12 1 33
AVCC AVCC AVCC AVCC CC-CDVCC CA-CBVCC AVCC
3.125V VA- AND V A+ CONNECT DIRECTLY TO SENSOR OUTPUTS 2.500V 1.875V 3.125V 2.500V 1.875V GAIN 2 GAIN 2
AVCC
3
VA-
VDRIVE G0 G1 G2 G3
27 40 39 38 37
VDRIVE 100nF 10F1
3V OR 5V SUPPLY
4
VA+
43 THIS REFERENCE SIGNAL MUST BE BUFFERED BEFORE IT CAN BE USED ELSEWHERE IN THE CIRCUIT 1F
SERIAL INTERFACE VREF A SCLK 34 35 32 31 24 36 23 22 21 VDRIVE MICROPROCESSOR/ MICROCONTROLLER
AD7262
VREF B
CS DOUTA DOUTB REFSEL
18 1F
3.125V VB- AND V B+ CONNECT DIRECTLY TO SENSOR OUTPUTS 2.500V 1.875V 3.125V 2.500V 1.875V GAIN 2 GAIN 2
CAL 9 VB+ PD0/DIN PD1 10 VB-
COUTD COUTC CC+ CD+ CB+ CA- CA+ CC- CD- CB-
PD2
COUTB COUTA
13 14 15 16
45 46 47 48
25 26 29 30
FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS
1THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE 2THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.
REQUIRED IN ALL SYSTEMS.
Figure 26. Typical Connection Diagram for the AD7262/AD7262-5 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2
Rev. 0 | Page 18 of 32
07606-026
AD7262
ANALOG SUPPLY +5V 10F1 100nF 100nF 100nF 100nF 100nF 100nF 10F1 COMPARATOR SUPPLY 3V TO 5V2 100nF
100nF 17 44
CC-CD-GND CA-CB-GND
5
AGND
6
AGND
8 19 42 28 2
AGND AGND AGND DGND
7 11 20 41 12 1 33
AVCC AVCC AVCC AVCC CC-CDVCC CA-CBVCC AVCC
3.125V VA- AND VA+ CONNECT DIRECTLY TO SENSOR OUTPUTS 2.500V 1.875V 3.125V 2.500V 1.875V GAIN 2 GAIN 2
AVCC
3
VA-
VDRIVE G0 G1 G2 G3
27 40 39 38 37
VDRIVE 100nF VDRIVE GAIN 2 SETUP SERIAL INTERFACE 10F1
3V OR 5V SUPPLY
4
VA+
43 THIS REFERENCE SIGNAL MUST BE BUFFERED BEFORE IT CAN BE USED ELSEWHERE IN THE CIRCUIT 1F
VREF A
SCLK
34 35 32 31 24 36 23 22 21 VDRIVE VDRIVE MICROPROCESSOR/ MICROCONTROLLER
AD7262
VREF B
CS DOUTA DOUTB REFSEL
18 1F
3.125V VB- AND VB+ CONNECT DIRECTLY TO SENSOR OUTPUTS 2.500V 1.875V 3.125V 2.500V 1.875V GAIN 2 GAIN 2
CAL 9 VB+ PD0/DIN PD1 10 VB-
COUTD COUTC CC+ CD+ CB+ CA+ CC- CD- CB- CA-
VDRIVE
PD2
COUTB COUTA
BOTH COMPARATORS AND ADCs POWERED ON
13 14 15 16
45 46 47 48
25 26 29 30
FAST PROPAGATION DELAY LOW POWER COMPARATOR INPUTS COMPARATOR INPUTS
1THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE 2THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.
REQUIRED IN ALL SYSTEMS.
Figure 27. Typical Connection Diagram for the AD7262/AD7262-5 in Pin-Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On
Rev. 0 | Page 19 of 32
07606-027
AD7262
Comparator Application Details
The comparators on the AD7262/AD7262-5 have been designed with no internal hysteresis, allowing users the flexibility to add external hysteretic if required for systems operating in noisy environments. If the comparators on the AD7262/AD7262-5 are used with external hysteresis, some external resistors and capacitors are required, as shown in Figure 28. The value of RF and RS, the external resistors, can be determined using the following equation, depending on the amount of hysteresis required in the application: VHYS = RS x C x _ C x VCC RS + RF
APPLICATION DETAILS
The AD7262/AD7262-5 have been specifically designed to meet the requirements of any motor control shaft position feedback loop. The devices can interface directly to multiple sensor types, including optical encoders, magneto resistive sensors, and Hall effect sensors. Flexible analog inputs that incorporate programmable gain ensure that identical board design can be used for a variety of sensors, which results in reduced design cycles and costs. The two simultaneous sampling ADCs are used to sample the sine and cosine outputs from the sensor. No external buffering is required between the sensor/transducer and the analog inputs of the AD7262/AD7262-5. The on-chip comparators can be used to monitor the pole sensors, which can be Hall effect sensors or the inner tracks from an optical encoder. Figure 29 shows how the AD7262/AD7262-5 can be used in a typical application. An optical encoder is shown in Figure 29, but other sensor types could as easily be used. Figure 29 indicates a typical application configuration only, and there are several other configurations that render equally effective results.
where Cx_CxVCC = CA_CBVCC or CC_CDVCC. The amount of hysteresis chosen must be sufficient to eliminate the effects of analog noise at the comparator inputs, which may affect the stability of the comparator outputs. The level of hysteresis required in any system depends on the noise in the system; thus, the values of RF and RS need to be carefully selected to eliminate any noise effects. To increase the level of hysteresis in the system, increase the value of RS or RF. For example, RF = 10 M, RS = 1 k give 330 V of hysteresis with a Cx_CxVCC of 3.3 V; if hysteresis is increased to 1 mV, RS = 3.1 k. In certain applications, a load capacitor (100 pF) may be required on the comparator outputs to suppress high frequency transient glitches.
RF RS SENSOR RS Cx- Cx+ COUTx
07606-028
Figure 28. Recommended Comparator Connection Diagram
Rev. 0 | Page 20 of 32
AD7262
COMP COMP AVCC VREF A
REF A VA+ VA- PGA T/H
BUF 12-BIT SUCCESSIVE APPROXIMATION ADC
AD7262
OUTPUT DRIVERS
DOUTA
CONTROL LOGIC
B VB+ VB- PGA T/H 12-BIT SUCCESSIVE APPROXIMATION ADC BUF VREF B H.E. CA_CBVCC Z U CA+ CA- CB+ CB- CA_CB_GND V W CC_CDVCC CC+ CC- CD+ CD- CC_CD_GND COMP COMP OUTPUT DRIVERS OUTPUT DRIVERS
SCLK CAL CS REFSEL G0 G1 G2 G3 VDRIVE OUTPUT DRIVERS DOUTB PD0/DIN PD1 PD2
COUTA COUTB
COMP
OUTPUT DRIVERS OUTPUT DRIVERS
COUTC COUTD
COMP
AGND
DGND
Figure 29. Typical System Connection Diagram with Optical Encoder
Rev. 0 | Page 21 of 32
07606-029
AD7262 MODES OF OPERATION
The AD7262/AD7262-5 allow the user to choose between two modes of operation, pin-driven mode and control register mode.
POWER-DOWN MODES
The AD7262/AD7262-5 offer the user a number of power-down options to enable individual device components to be powered down independently. These options can be chosen to optimize the power dissipation for different application requirements. The power-down modes can be selected by either programming the device via the control register or by driving the PD pins to the appropriate logic levels. By setting the PD pins to a logic low level when in pin-driven mode, all four comparators and both ADCs can be powered down. The PD2 and PD0 pins must be set to logic high and the PD1 pin set to logic low to power up all circuitry on the AD7262/AD7262-5. The PD pin configurations for the various power-down options are outlined in Table 7.
Table 7. Power-Down Modes
PD2 PD1 PD0 Comparator A, Comparator B Comparator C, Comparator D ADC A, ADC B
PIN-DRIVEN MODE
In pin-driven mode, the user can select the gain of the PGA, the power-down mode, internal or external reference, and initiate a calibration of the offset for both ADC A and ADC B. These functions are implemented by setting the logic levels on the gain pins (G3 to G0), the power-down pins (PD2 to PD0), the REFSEL pin, and the CAL pin, respectively. The logic state of Pin G3 to Pin G0 determines which mode of operation is selected. Pin-driven mode is selected if at least one of the gain pins is set to a logic high state. Alternatively, if all four gain pins are connected to a logic low, the control register mode of operation is selected.
GAIN SELECTION
The on-board PGA allows the user to select from 14 programmable gain stages: x1, x2, x3, x4, x6, x8, x12, x16, x24, x32, x48, x64, x96, and x128. The PGA accepts fully differential analog signals and provides three key functions, which include selecting gains for small amplitude input signals, driving the ADCs switched capacitive load, and buffering the source from the switching effects of the SAR ADCs. The AD7262/AD7262-5 offer the user great flexibility in user interface, providing gain selection via the control register or by driving the gain pins to the desired logic state. The AD7262/AD7262-5 have four gain pins, G3, G2, G1 and G0, as shown in Figure 3. Each gain setting is selected by setting up the appropriate logic state on each of the four gain pins, as outlined in Table 6. If all four gain pins are connected to a logic low level, the part is put in control register mode and the gain settings are selected via the control register.
Table 6. Gain Selection
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 G1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 G0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Gain Software control via control register 1 2 3 4 6 8 12 16 24 32 48 64 96 128
0 0 0 0 1 1 11
1
0 0 1 1 0 0 11
0 1 0 1 0 1 11
Off Off Off On On On Off
Off Off On Off On On Off
Off On Off Off Off On Off
PD2 = PD1 = PD0 = 1 resets the AD7262/AD7262-5 when in pin-driven mode only.
The AVCC and VDRIVE supplies must continue to be supplied to the AD7262/AD7262-5 when the comparators are powered up but the ADCs are powered-down. External diodes can be used from the CA_CBVCC and/or CC_CDVCC to both the AVCC and the VDRIVE supplies to ensure they retain a supply at all instances. The AD7262/AD7262-5 can be reset in pin-driven mode only by setting the PDx pins to a logic high state. When the device is reset, all the registers are cleared and the four comparators and the two ADCs are left powered down. In normal mode of operation with the ADCs and comparators powered on, the CA_CBVCC/CC_CDVCC supply and the AVCC supply can be at different voltage levels, as indicated in Table 1. When the comparators on the AD7262/AD7262-5 are in powerdown mode, and the CA_CBVCC/CC_CDVCC supplies are at a potential 0.3 V greater than or less than the AVCC supply, the supplies consume more current than would be the case if both sets of supplies were at the same potential. This configuration does not damage the AD7262/AD7262-5 but results in additional current flowing in any or all of the AD7262/AD7262-5 supply pins. This is due to ESD protection diodes within the device. In applications where power consumption in power-down mode is critical, it is recommended that the CA_CBVCC/CC_CDVCC supply and the AVCC supply be held at the same potential.
Rev. 0 | Page 22 of 32
AD7262
Power-Up Conditions
On power-up, the status of the gain pins determine which mode of operation is selected, as outlined in the Gain Selection section. All registers are set to 0 by default. If the AD7262/AD7262-5 are powered up in pin-driven mode, the gain pins and the PDx pins should be configured to the appropriate logic states and a calibration initiated if required. Alternatively, if the AD7262/AD7262-5 are powered up in control register mode, the comparators and ADCs are powered down and the default gain is 1. Thus, powering up in control register mode requires a write to the device to power up the comparators and the ADCs. It takes 15 s to power up the AD7262/AD7262-5 when using an external reference. When the internal reference is used, 240 s are required to power up the AD7262/AD7262-5 with a 1 F decoupling capacitor. These functions can also be implemented by setting the logic levels on the gain pins, the power-down pins, and the CAL pin, respectively. The control register can also be used to read the offset and gain registers. Data is loaded from the PD0/DIN pin of the AD7262/AD7262-5 on the falling edge of SCLK when CS is in a logic low state. The control register is selected by first writing the appropriate four WR bits, as outlined in Table 10. The 12 data bits must then be clocked into the control register of the device. Thus, on the 16th falling SCLK edge, the LSB is clocked into the device. One more SCLK cycle is then required to write to the internal device registers. In total, 17 SCLK cycles are required to successfully write to the AD7262/AD7262-5. The data is transferred on the PD0/DIN line while the conversion result is being processed. The data transferred on the DIN line corresponds to the AD7262/ AD7262-5 configuration for the next conversion. Only the information provided on the 12 falling clock edges after the CS falling edge and the initial four write address bits is loaded to the control register. The PD0/DIN pin should have a logic low state for the four bits RD3 to RD0 when using the control register to select the power-down modes or gain setting or when initializing a calibration. The RD bits should also be set to a logic low level to access the ADC results from both DOUTA and DOUTB. The power-up status of all bits is 0 and the MSB denotes the first bit in the data stream. The bit functions are outlined in Table 8 and Table 9.
LSB Bit 0 G0
CONTROL REGISTER
The control register on the AD7262/AD7262-5 is a 12-bit read and write register, which is used to control the device when not in pin-driven mode. The PD0/DIN pin serves as the serial DIN pin for the AD7262/AD7262-5 when the gain pins are set to 0 (that is, the part is not in pin-driven mode). The control register can be used to select the gain of the PGAs, the powerdown modes, and the calibration of the offset for both ADC A and ADC B. When operating in the control register mode, PD1 and PD2 should be connected to a low logic state.
Table 8. Control Register Bits
MSB Bit 11 RD3 Bit 10 RD2 Bit 9 RD1 Bit 8 RD0 Bit 7 CAL Bit 6 PD2
Bit 5 PD1
Bit 4 PD0
Bit 3 G3
Bit 2 G2
Bit 1 G1
Table 9. Control Register Bit Function Description
Bits 11 to 8 7 6 to 4 3 to 0 Mnemonic RD3 to RD0 CAL PD2 toPD0 G3 to G0 Description Register address bits. These bits select which register the subsequent read is from. See Table 11. Setting this bit high initiates an internal offset calibration. Once the calibration is completed, this pin can be reset low, and the internal offset, which is stored in the on-chip offset registers, is automatically removed from the ADC results. Power-down bits. These bits select which power-down mode is programmed. See Table 7. Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.
Table 10. Write Address Bits
WR3 0 WR2 0 WR1 0 WR0 1 Read Register Addressed Control register
CS
t2
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31
t8
DOUTA PD0/DIN
WR3
THREE-STATE
tQUIET
DB11 DB10 DB0
07606-030
t13
WR2 WR1 WR0 RD3 RD2 RD1
t14
RD0 CAL PD2 PD1 PD0 G3 G2 G1 G0
THREE-STATE
THREESTATE
Figure 30. Timing Diagram for a Write Operation to the Control Register
Rev. 0 | Page 23 of 32
AD7262
Table 11. Read and Write Register Addresses
ON-CHIP REGISTERS
The AD7262/AD7262-5 contain a control register, two offset registers for storing the offsets for each ADC, and two external gain registers for storing the gain error. The control register and the offset and gain registers are read and write registers. On power-up, all registers in the AD7262/AD7262-5 are set to 0.
Addressing the On-Chip Registers Writing to a Register
Data is loaded from the PD0/DIN pin of the AD7262/AD7262-5 on the falling edge of SCLK when CS is in a logic low state. Four address bits and 12 data bits must be clocked into the device. Thus, on the 16th falling SCLK edge, the LSB is clocked into the AD7262/AD7262-5. One more SCLK cycle is then required to write to the internal device registers. In total, 17 SCLK cycles are required to successfully write to the AD7262/AD7262-5. The control and offset registers are 12-bits registers; the gain registers are 7-bit registers. When writing to a register, the user must first write the address bits corresponding to the selected register. Table 11 shows the decoding of the address bits. The four RD bits are written MSB first, that is, RD3 followed by RD2, RD1, and RD0. The AD7262/AD7262-5 decodes these bits to determine which register is being addressed. The subsequent 12 bits of data are written to the addressed register. When writing to the external gain registers, the seven bits of data immediately after the four address bits are written to the register. However, 17 SCLK cycles are still required, and the PD0/DIN pin of the AD7262/AD7262-5 should be tied low for the five additional clock cycles.
RD3 0 0 0 0 0 0
RD2 0 0 0 0 1 1
RD1 0 0 1 1 0 0
RD0 0 1 0 1 0 1
Comment ADC result (default) Control register Offset ADC A internal Offset ADC B internal Gain ADC A external Gain ADC B external
Reading from a Register
The internal offset of the device, which has been measured by the AD7262/AD7262-5 and stored in the on-chip registers during the calibration, can be read back by the user. The content of the external gain registers can also be read. To read the content of any register, the user must first write to the control register by writing 0001 to the WR3 to WR0 bits via the PD0/DIN pin, as outlined in Table 10. The next four bits in the control register are the RD bits, which are used to select the desired register from which to read. The appropriate 4-bit address for each of the offset and gain registers is outlined in Table 11. The remaining eight SCLK cycles bits are used to set the remaining bits in the control register to the desired state for the next ADC conversion. The 19th SCLK falling edge clocks out the first data bit of the digital code corresponding to the value stored in the selected internal device register on the DOUTA pin. DOUTB outputs the conversion result from ADC B. Once the selected register has been read, the control register must be reset to output the ADC results for future conversions. This is achieved by writing 0001 to the WR3 to WR0 bits, followed by 0000 to the RD bits. The remaining eight bits in the control register should then be set to the required configuration for the next ADC conversion.
CS
t2
SCLK DOUTA PD0/DIN
RD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31
t8 tQUIET
THREE-STATE
07606-031
THREE-STATE
t13
RD2 RD1 RD0 MSB DB10 DB9
t14
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB11A
DB10A
DB0A
THREESTATE
Figure 31. Timing Diagram for Writing to a Register
CS
t2
SCLK DOUTA PD0/DIN
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 30 31
t8 tQUIET
RD3 RD2 RD1 RD0 0 0 0 0 0 0 0 0
THREE-STATE
0
1
THREE-STATE
Figure 32. Timing Diagram for a Read Operation with PD0/DIN as an Input
Rev. 0 | Page 24 of 32
07606-032
t13
t14
DB11A
DB10A
DB0A
THREESTATE
AD7262 SERIAL INTERFACE
Figure 33 and Figure 34 show the detailed timing diagrams for the serial interfacing of the AD7262/AD7262-5. The serial clock provides the conversion clock and controls the transfer of information from the AD7262/AD7262-5 after the conversion. The AD7262/AD7262-5 has two output pins corresponding to each ADC. Data can be read from the AD7262/AD7262-5 using both DOUTA and DOUTB. Alternatively, a single output pin of the user's choice can be used. The SCLK input signal provides the clock source for the serial interface. The falling edge of CS puts the track-and-hold into hold mode, at which point the analog input is sampled. The conversion is also initiated at this point and requires a minimum of 19 SCLKs to complete. The DOUTx lines remain in three-state while the conversion is taking place. On the 19th SCLK falling edge, the AD7262/AD7262-5 return to track mode and the DOUTA and DOUTB lines are enabled. The data stream consists of 12 bits of data, MSB first. The MSB of the conversion result is clocked out on the 19th SCLK falling edge to be read by the microcontroller or DSP on either the subsequent SCLK falling edge (20th falling edge) or the 20th SCLK rising edge. The choice of whether to read on the rising or falling SCLK edge depends on the SCLK frequency being used. When the maximum SCLK frequency of 40 MHz is used with a VDRIVE voltage of 5 V, the maximum specified access time (t4) is 23 ns, resulting in 2 ns of setup time, which may not be sufficient for most DSPs or microcontrollers. Under these conditions, it is recommended to use the rising SCLK edge to read the data. In this case, the MSB of the conversion result is clocked out on the 19th SCLK falling edge to be read on the 20th SCLK rising edge, as shown in Figure 33. The remaining data is then clocked out by subsequent SCLK falling edges. When using a 40 MHz SCLK frequency, the 20th falling clock edge on the serial clock clocks out the second data bit, which is provided for reading on the 21st SCLK rising edge. The remainder of the 12-bit result follows, with the final bit in the data transfer being valid on the 31st rising edge. The LSB is provided on the 30th falling clock edge. An alternative to reading on the rising SCLK edge is to use a slower SCLK frequency. If a slower SCLK frequency is used, for example 32 MHz with the AD7262, this will enable reading on the subsequent falling SCLK edge after the data has been clocked out, as illustrated in Figure 35. A throughput rate of 1 MSPS can still be achieved for the AD7262 when a 32 MHz SCLK frequency is used. The remaining data is then clocked out by subsequent SCLK falling edges. When using a 32 MHz or less SCLK frequency with the AD7262 or when using the AD7262-5, the 20th falling clock edge on the serial clock has the MSB provided for reading and also clocks out the second data bit. The remainder of the 12-bit result follows, with the final bit in the data transfer being valid on the 31st falling edge. The LSB is provided on the 30th falling clock edge. On the rising edge of CS, DOUTA and DOUTB go back into threestate. If CS is not brought high after 31 SCLKs but is instead held low for an additional 12 SCLK cycles, the data from ADC B is output on DOUTA after the ADC A result. Likewise, the data from ADC A is output on DOUTB after the ADC B result. This is illustrated in Figure 34, which shows the DOUTA example. In this case, the DOUT line in use goes back into threestate on the 45th SCLK falling edge or the rising edge of CS, whichever occurs first. If the falling edge of SCLK coincides with the falling edge of CS, the falling edge of SCLK is not acknowledged by the AD7262 and the next falling edge of SCLK is the first one registered after the falling edge of CS.
Rev. 0 | Page 25 of 32
AD7262
FIRST DATA BIT CLOCKED OUT ON THE 19TH FALLING EDGE CS FIRST DATA BIT READ ON 20TH RISING EDGE
t2
SCLK 1 2 3 4 5 18 19 20 21 22 29 30 31
t8
t4
DOUTA THREE-STATE DB11 A DB10 A DB9A
t5
DB1A DB0 A THREESTATE THREESTATE
07606-033
DOUTB
THREE-STATE
DB11 B
DB10 B
DB9B
DB1B
DB0 B
Figure 33. Serial Interface Timing Diagram When Reading Data on the 20th Rising SCLK Edge with a 40 MHz SCLK
CS
SCLK
1
2
18
19
20
21
29
30
31
43
44
45
t10
DOUTA THREE-STATE DB13 A DB12 A DB1 A DB0 A DB13 B DB12 B DB1B DB0B THREESTATE
07606-034
Figure 34. Reading Data from Both ADCs on One DOUT Line with 45 SCLKs
FIRST DATA BIT CLOCKED OUT ON THIS EDGE CS
FIRST DATA BIT READ ON THIS EDGE
t8 t2 t6
2 3 4 5 18 19 20 21 29 30 31 1
SCLK
t3
DOUTA THREE-STATE DB11 A
t7
t4
DB10 A DB9 A
t5
DB1 A
t9
DB0A
tQUIET
THREESTATE THREESTATE
07606-035
DOUTB
THREE-STATE
DB11 B
DB10 B
DB9 B
DB1 B
DB0B
Figure 35. Serial Interface Timing Diagram When Reading Data on the Falling SCLK Edge with a Slow SCLK Frequency
Rev. 0 | Page 26 of 32
AD7262 CALIBRATION
INTERNAL OFFSET CALIBRATION
The AD7262/AD7262-5 allow the user to calibrate the device offset using the CAL pin. This is achieved by setting the CAL pin to a high logic level, which initiates a calibration on the next CS falling edge. The calibration requires one full conversion cycle, which contains a CS falling edge followed by 19 SCLKs to complete. The CAL pin can remain high for more than one conversion if desired, and the AD7262/AD7262-5 continue to calibrate. The CAL pin should only be driven high when the CS pin is high or after 19 SCLK cycles have elapsed when CS is low (that is, between conversions). The CAL pin must be driven high t12 ns before CS goes low. If the CS pin goes low before the t12 has elapsed, the calibration result is inaccurate for the current conversion, but, provided that the CAL pin remains high, the subsequent calibration conversion is correct. If the CAL pin is set to a logic high state during a conversion, that conversion result is corrupted. Provided that the CAL pin has been held high for a minimum of one conversion, and once t12 and t11 have been adhered to, the calibration is complete after the 19th SCLK cycle, and the CAL pin can be driven to a logic low state. The next CS falling edge after the CAL pin has been driven to a low logic state initiates a conversion of the differential analog input signal for both ADC A and ADC B. Alternatively, one can use the control register to initiate an offset calibration. This is done by setting the CAL bit in the control register to 1. The calibration is then initiated on the next CS falling edge, but the current conversion is corrupted. The ADCs on the AD7262/AD7262-5 must remain fully powered up to complete the internal calibration. The AD7262/AD7262-5 registers store the offset value that can be accessed easily by the user (see the Reading from a Register section). When the device is calibrating, the differential analog inputs for each respective ADC are shorted together internally and a conversion is performed. A digital code representing the offset is stored internally in the offset registers, and subsequent conversion results have this measured offset removed. When the AD7262/AD7262-5 are calibrated, the calibration results stored in the internal device registers are only relevant for the particular PGA gain selected at the time of calibration. If the PGA gain is changed, the AD7262/AD7262-5 must be recalibrated. If the device is not recalibrated when the PGA gain is changed, the offset for the previous gain setting continues to be removed from the digital output code, which may lead to inaccuracies. The offset range, which can be calibrated for, is 128 least significant bits at a gain of 1. The maximum offset voltage, which can be calibrated for, is reduced as the gain of the PGA is increased. Table 12 details the maximum offset voltage, which can be removed by the AD7262/AD7262-5 without compromising the available digital output code range. The least significant bit size is AVCC/2BITs, which is 5/4096 or 1.22 mV for the AD7262/ AD7262-5. The maximum removable offset voltage is given by
128 LSB x 1.22 mV Gain
Table 12. Offset Range
Gain 1 2 3 32
1
Maximum Removable Offset Voltage 156.16 mV 78.08 mV 52.053 mV 4.88 mV 1
This is the maximum removable offset for PGA gain 32.
t11 t12
CAL
t8
CS
t2
SCLK
1 2 3
t6
19 20 21 30 31 1 2 3 19 20 21
t7
Figure 36. Calibration Timing Diagram
Rev. 0 | Page 27 of 32
07606-036
AD7262
ADJUSTING THE OFFSET CALIBRATION REGISTERS
The internal offset calibration register can be adjusted manually to compensate for any signal path offset from the sensors to the ADC. Here, no internal calibration is required, and the CAL pin can remain at a low logic state. By changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. To determine the digital code to be written to the offset register 1. 2. 3. Configure the sensor to its offset state. Perform a number of conversions using the AD7262/ AD7262-5. Take the mean digital output code from both DOUTA and DOUTB. This is a 12-bit result and the offset register is 12 bits; thus, the result can be stored directly in the offset register. Write the digital code to the offset registers to calibrate the AD7262/AD7262-5.
SYSTEM GAIN CALIBRATION
The AD7262/AD7262-5 also allow the user to write to an external gain register, thus enabling the removal of any overall system gain error. Both ADC A and ADC B have independent external gain registers, allowing the user to calibrate independently the gain on both ADC A and ADC B signal paths. The gain calibration feature can be used to implement accurate gain matching between ADC A and ADC B. The system calibration function is used by setting the sensors to which the AD7262/AD7262-5 are connected to a 0 gain state. The AD7262/AD7262-5 convert this analog input to a digital output code, which corresponds to the system gain and is available on the DOUTx pins. This digital output code can then be stored in the appropriate external register. For details on how to write to a register, see the Writing to a Register section and Table 11. The gain calibration register contains seven bits of data. By changing the contents of the gain register, different amounts of gain on the analog input signal can be compensated for. The MSB is a sign bit, while the remaining six bits store the multiplication factor, which is used to adjust the analog input range. The gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. Increasing the gain register multiplication factor compensates for a larger analog input range, and decreasing the gain register multiplier compensates for a smaller analog input range. Each bit in the gain calibration register has a resolution of 2.4 x 10-4 V (1/4096). A maximum of 1.538% of the analog range can be calibrated for. The multiplier factor stored in the gain register can be decoded as outlined in Table 13. The gain registers can be cleared by writing all 0s to each register, as described in the Writing to a Register section. For accurate gain calibration, both the positive and negative full-scale digital output codes should be measured prior to determining the multiplication factor that is written to the gain register.
4.
If a +10 mV offset is present in the analog input signal and the gain of the PGA is 2, the code that needs to be written to the offset register to compensate for the offset is
+10 mV (1.22 mV / 2 = 16.39 = 0000 0001 0000
If a - 10 mV offset is present in the analog input signal and the gain of the PGA is 2, the code that needs to be written to the offset register to compensate for the offset is -10 mV = -16.39 = 1000 0001 0000 (305 V/ 2)
Table 13. Decoding of Multiplication Factors for Gain Calibration
Analog Input V VIN max VIN max - 244 V VIN max - (63 x 244 V) VIN max VIN max + 244 V VIN max + (63 x 244 V) Digital Gain Error LSB 0 LSB -2 LSB -126 LSB 0 LSB +2 LSB +126 LSB Gain Register Code (Sign bit + 6 bits) 0 000000 0 000001 0 111111 1 000000 1 000001 1 111111 Multiplier Equation (1 x/4096) 1 - 0/4096 1 - 1/4096 1 - 63/4096 1 + 0/4096 1 + 1/4096 1 + 63/4096 Multiplier Value 1 0.999755859 0.98461914 1 1.000244141 1.015380859 Comments Sign bit = 0, which implies negative sign in multiplier equation Sign bit = 0, which implies negative sign in multiplier equation Sign bit = 0, which implies negative sign in multiplier equation Sign bit = 1, which implies plus sign in multiplier equation Sign bit = 1, which implies plus sign in multiplier equation Sign bit = 1, which implies plus sign in multiplier equation
Rev. 0 | Page 28 of 32
AD7262 MICROPROCESSOR INTERFACING
The serial interface on the AD7262/AD7262-5 allows the parts to be directly connected to a range of different microprocessors. This section explains how to interface the AD7262/AD7262-5 with the Analog Devices, Inc., Blackfin(R) DSP, the ADSP-BF537.
Table 14. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1)
Setting RCKFE = 1 LRFS = 1 RFSR = 1 IRFS = 1 RLSBIT = 0 RDTYPE = 00 IRCLK = 1 RSPEN = 1 SLEN = 11110 TFSR = RFSR = 1 Description Sample data with falling edge of RSCLK Active low frame signal Frame every word Internal receive frame sync (RFS) used Receive MSB first Zero fill Internal receive clock Receive enabled 31-bit data-word
AD7262/AD7262-5 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interface directly to the AD7262/AD7262-5 without any glue logic required. The VDRIVE pin of the AD7262/AD7262-5 takes the same supply voltage as that of the ADSP-BF53x. This allows the ADC to operate at a higher supply voltage than its serial interface and, therefore, the ADSP-BF53x, if necessary. The availability of secondary receive registers on the serial ports of the Blackfin DSPs means only one serial port is necessary to read from both DOUT pins simultaneously. Figure 37 shows both DOUTA and DOUTB of the AD7262/AD7262-5 connected to Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive Configuration 1 register and SPORT0 Receive Configuration 2 register should be set up as outlined in Table 14 and Table 15.
AD72621
DOUTA SCLK CS DOUTB VDRIVE SERIAL DEVICE B (SECONDARY)
Table 15. The SPORT0 Receive Configuration 2 Register (SPORT0_RCR2)
Setting RXSE = 1 Description Secondary side enabled
ADSP-BF53x1
SERIAL DEVICE A (PRIMARY) SPORT0 DR0PRI RCLK0 RFS0 DR0SEC
A Blackfin driver for the AD7262/AD7262-5 is available to download at www.analog.com.
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 37. Interfacing the AD7262 to the ADSP-BF53x
07606-037
VDD
Rev. 0 | Page 29 of 32
AD7262 APPLICATION HINTS
GROUNDING AND LAYOUT
The analog and digital supplies to the AD7262/AD7262-5 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AD7262/AD7262-5 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All five AGND pins of the AD7262/AD7262-5 should be sunk in the AGND plane. Digital and analog ground planes should be joined in only one place. If the AD7262/AD7262-5 are in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point, that should be established as close as possible to the ground pins on the AD7262/AD7262-5. Avoid running digital lines under the device because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7262/AD7262-5 to avoid noise coupling. The power supply lines to the AD7262/ AD7262-5 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital ground, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is the best method but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 F tantalum capacitors in parallel with 100 nF capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 F capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
PCB DESIGN GUIDELINES FOR LFCSP
The land on the chip scale packages (CP-48-1) are rectangular. The PCB pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width, thereby having a portion of the pad exposed. To ensure that the solder joint size is maximized, the land should be centered on the pad. The bottom of the chip scale package has a thermal pad. The thermal pad on the PCB should be at least as large as the exposed pad. On the PCB, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. To improve thermal performance of the package, use thermal vias on the PCB, incorporating them into the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the PCB thermal pad to AGND.
Rev. 0 | Page 30 of 32
AD7262 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 38. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
0.75 0.60 0.45
1.60 MAX
48 1
9.20 9.00 SQ 8.80
37 36
PIN 1
1.45 1.40 1.35
0.15 0.05
TOP VIEW
0.20 0.09 7 3.5 0 0.08 COPLANARITY
(PINS DOWN)
7.20 7.00 SQ 6.80
12 13 24
25
SEATING PLANE
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7262BCPZ 1 AD7262BCPZ-RL71 AD7262BCPZ-51 AD7262BCPZ-5-RL71 AD7262BSTZ1 AD7262BSTZ-RL71 AD7262BSTZ-51 AD7262BSTZ-5-RL71 EVAL-AD7262EDZ1 EVAL-CED1Z1
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Development Board
Z = RoHS Compliant Part. Rev. 0 | Page 31 of 32
051706-A
ROTATED 90 CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
Package Option CP-48-1 CP-48-1 CP-48-1 CP-48-1 ST-48 ST-48 ST-48 ST-48
061208-A
SEATING PLANE
0.20 REF
COPLANARITY 0.08
THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS.
AD7262 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07606-0-7/08(0)
Rev. 0 | Page 32 of 32

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